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HANBit
HDD16M64D8W
DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., DIMM, Part No. HDD16M64D8W
GENERAL DESCRIPTION
The HANBiT HDD16M64D8W is 16M bit x 64 Double Data Rate SDRAM high density memory modules. The HANBiT HDD16M64D8W consists of eight CMOS 16M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD16M64D8W is Dual In-line Memory Modules and intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURES
* Part Identification
HDD16M64D8W - 10A HDD16M64D8W - 13A HDD16M64D8W - 13B : 100MHz (CL=2) : 133MHz (CL=2) : 133MHz (CL=2.5)
* Power supply : VDD: 2.5V 0.2V, VDDQ: 2.5V 0.2V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height 1250 mil, double sided component
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PIN ASSIGNMENT
P1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol VREF DQ1 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 *CB0 *CB1 VDD *DQS8 A0 *CB2 VSS *CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 PIN 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Symbol DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC PIN 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 131 132 133 134 135 136 137 Symbol NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 DM1 VDDQ *BA2 DQ20 *A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3 A3 VSS DQ31 *CB4 *CB5 VDDQ CK0 PIN 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 P2
HDD16M64D8W
Symbol /CK0 VSS *DM8 A10 *CB6 VDDQ *CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDDQ /CS0 */CS1 DM5 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6 DQ54 DQ55
PIN 172 173 174 175 176 177 178 179 180 181 182 183 184
Symbol VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
* These pins should be NC in the system which does not support SPD PIN A0~A12 BA0~BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS7 DM0~DM7 CK0~CK2,/CK0~/CK2 CKE0 /CS0 /RAS
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PIN DESCRIPTION Address input Bank Select Address Data input/output Check bit(Data input/output) Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row Address strobe
2
PIN VDD VDDQ VREF VDDSPD VSS SA0~SA2 SDA SCL /WE VDDID
PIN DESCRIPTION Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(3.3) Ground Address in EEPROM Serial data I/O Serial clock Write enable VDD indentification flag
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/CAS Column Address strobe NC
HDD16M64D8W
No connection
FUNCTIONAL BLOCK DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation SYMBOL VIN, VOUT VDD VDDQ TSTG PD RATING -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 8.0
HDD16M64D8W
UNTE V V V C W mA
Short circuit current IOS 50 Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70C) )
PARAMETER Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage(system) Input High Voltage Input Low Voltage Input Voltage Level, CK and /CK inputs Input Differential Voltage, CK and /CK inputs Input crossing point voltage, CK and CK inputs Input leakage current Output leakage current Output High current (VOUT = 1.95V) Output Low current (VOUT = 0.35V) Output High Current(Half strengh driver) Output High Current(Half strengh driver) SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) VIx (DC) I LI I OZ I OH I OL IOH IOL MIN 2.3 2.3
VDDQ/2-50mV
MAX 2.7 2.7
VDDQ/2+50mV
UNIT V V V V V V V V V uA uA mA mA mA mA
NOTE
1 2 4 4
VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9
VREF + 0.04 VREF + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.35 2 5
3 5
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards.
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DDR SDRAM IDD SPEC TABLE
SYMBOL IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 Normal IDD6 Low power IDD7A 8 2640 8 2400 8 2400 B3(DDR333@CL=2.5) 840 1040 28 200 144 280 440 1280 1216 1480 16 A2(DDR266@CL=2) 760 960 24 176 120 280 440 1136 1040 1480 16
HDD16M64D8W
B0(DDR266@CL=2.5) 760 960 24 176 120 280 440 1136 1040 1480 16
UNIT mA mA mA mA mA mA mA mA mA mA mA mA mA
NOTE
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC OPERATING CONDITIONS
PARAMETER/ CONDITION STMBOL MIN MAX UNIT NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs
VIH (AC) VIL (AC) VID (AC) VIX (AC)
VREF + 0.31 VREF - 0.31 0.7 0.5*VDDQ-0.2 VDDQ+0.6 0.5*VDDQ+0.2 V V V
3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a VREF envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS
PARAMETER Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition VALUE 0.5 * VDDQ 1.5 0.5 VREF+0.31/VREF-0.31 VREF VTT See Load Circuit UNIT V V V/ns V V V V NOTE
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HDD16M64D8W
INPUT/OUTPUT CAPACITANCE
DESCRIPTION
(VDD = 2.5V, VDDQ = 2.5V, TA = 25C, f = 1MHz) SYMBOL MIN MAX UNITS
Input Capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE ) Input Capacitance(CKE0) Input Capacitance( CS0) Input Capacitance( CLK0, CLK1,CLK2 ) Data & DQS input/output Capacitance(DQ0~DQ63) Input Capacitance(DM0~DM8)
CIN1 CIN2 CIN3 CIN4 COUT1 CIN5
49 42 42 22 6 6
57 50 50 25 8 8
pF pF pF pF pF pF
AC TIMMING PARAMETERS & SPECIFICATIONS (THESEACCHARICTERISTICSWERETESTEDON THECOMPONENT)
DDR200 PARAMETER SYMBOL -10A MIN MAX MIN DDR266A -13A MAX MIN DDR266B -13B MAX UNIT NOTE
Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2.5
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tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tCK
70 80 48 20 20 15 2 1 1 10 12 12
6
65 75 120K 45 20 20 15 2 1 1 7.5 7.5 12 12 120K
65 75 45 20 20 15 2 1 1 10 7.5 12 12 120K
ns ns ns ns ns ns tCK tCK tCK ns ns
1 1,2 1,2 3 3 3 3 2
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Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble Data out high impedence time from CK-/CK CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in falling edge to CK rising-setup time DQS-in falling edge to CK rising hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active command Exit self refresh to read command Refresh interval time Output DQS valid window DQS write postamble time Notes : tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tHZQ tDQSS tWPRES tWPREH tDSS tDSH tDQSH tDQSL tDSC tIS tIH tMRD tDS tDH tDIPW tPDEX tXSW tXSA tXSR tREF tQH tWPST 0.45 0.45 -0.8 -0.8 0.9 0.4 -0.8 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 1.1 1.1 16 0.6 0.6 2 10 116 80 200 15.6 0.35 0.25 1.1 0.55 0.55 +0.8 +0.8 +0.6 1.1 0.6 +0.8 1.25 0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 95 75 200 15.6 0.35 0.25 1.1 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25
HDD16M64D8W
0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 1.1 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25 tCK tCK ns ns ns tCK tCK ns tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns 75 200 15.6 0.35 0.25 ns Cycle us tCK tCK 4 1 3 2
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP) ) of the PLL and the half jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate tIS (V/ns) (ps) 0.5 0 0.4 +50 0.3 +100 tIH (ps) 0 +50 +100
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HDD16M64D8W
This derating table is used to increase tDS/tDH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate tIS (V/ns) (ps) 0.5 0 0.4 +75 0.3 +150 tIH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level tDS (mV) (ps) +50 280 tDH (ps) +50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate tDS (ns/V) (ps) 0 0 0.25 +50 0.5 +100 tDH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
COMMAND TRUTH TABLE (V=VALID, X=DO CARE, H=LOGIC HIGH, L=LOGIC LOW) T
COMMAND CKE n-1 CKE n /CS /RAS /CAS /WE DM BA 0,1 A10/ AP A11 A9~A0 NOTE
Register Register
Extended MRS Mode register set Auto refresh Entry Exit
H H H L H
X X H L H X
L L L L H L
L L L H X L
L L L H X H
L L H H X H
X X X X X V
OP code OP code X X Row address L Column Address H (A0 ~ A9) Column Address H (A0 ~ A9) X V X L H X X X
1,2 1,2 3 3 3 3
Refresh
Self refresh
Bank active & Row Addr. Read & column address Write & column address Burst Stop Precharge Bank selection All banks Entry Exit Entry Auto disable Auto eable Auto disable Auto enable precharge precharge precharge precharge
4 4 4 4,6 7 5
H
X
L
H
L
H
X
V
H H X L H L L H H H L H X X L H L L L H L X H L H L X V X X H
8
L X V
H H X V X X H
L L X V X X H
X X X X X
Clock suspend or active power down Precharge power down mode
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Exit DM No operation command Note : L H H X H L H H L X V X X H X H X H X V X V X V X
HDD16M64D8W
X X
8 9 9
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
PACKAGE DIMENSIONS
Unit : mm
Front - Side
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Rear-Side
HDD16M64D8W
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
MAX.frq
HDD16M64D8W-10A HDD16M64D8W -13A HDD16M64D8W -13B
128MByte 128MByte 128MByte
16M x 64 16M x 64 16M x 64
184PIN DIMM 184PIN DIMM 184PIN DIMM
4K 4K 4K
2.5V 2.5V 2.5V
DDR DDR DDR
100MHz/CL2 133MHz/CL2 133MHz/CL2.5
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